MODELING OF NBTI DEGRADATION IN P-CHANNEL VDMOSFETS

Nikola Mitrovic; Danijel Danković; Zoran Prijić; Ninoslav Stojadinović

doi:10.5937/jaes0-26760

Nikola Mitrovic University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia
Danijel Danković University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia
Zoran Prijić University of Nis, Faculty of Electronic Engineering, Department of Microelectronics, Nis, Serbia
Ninoslav Stojadinović Serbian Academy of Sciences and Arts (SASA), Belgrade, Serbia

DOI: https://doi.org/10.5937/jaes0-26760

Keywords: reliability, VDMOS power transistors, threshold voltage, modeling

Abstract

This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analised. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.

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